1. Field of the Invention
The present invention relates to a gate array large-scale integrated circuit (LSI) device, more particularly, to a gate array LSI device which uses, as an inner gate circuit, a circuit having PNP-type transistors at the input portion thereof and an off-buffer circuit at the output portion thereof, thereby increasing the degree of freedom of the logical design of the gate array LSI device.
2. Description of the Prior Art
In recent years, semiconductor integrated circuit devices have been made increasingly dense so as to decrease the overall cost and increase the reliability of final electronic devices. An increased density of the semiconductor integrated circuit devices, however, means a more complex arrangement of connection lines on the semiconductor chip and a resultantly greater capacitance of the connection lines. This in turn has an adverse effect on the switching speed of inner gate circuits and so on.
In a gate array LSI device, the connection paths within the semiconductor chip are determined by automatic wiring processing of a computer aided design (CAD) system. Therefore, it is difficult to learn the specific lengths of the inner connection lines. It is also difficult to learn the specific maximum value of the number of gate circuits connected to the output of one inner gate circuit, i.e., the maximum fan-out number. Therefore, it is preferabley to use inner gate circuits whose switching speed and so on are not affected by variation of the length of the connection lines and of the fan-out number.
In a conventional gate array LSI device, each inner gate circuit used therein comprises an input stage formed of a NPN-type multi-emitter transistor and an output stage formed of a single NPN-type inverter transistor.
In such a conventional gate array LSI device, it is necessary to pull-down, by the output stage transistor, a large amount of current from the power source through each emitter of the multi-emitter transistor of the corresponding input terminal of the next stage. Therefore, it is impossible to increase the fan-out number of each of the pre-stage gate circuits. Moreover, since the output stage of each inner gate circuit is formed of a single inverter transistor, the rise time of the output signal, apart from the fall time thereof, varies greatly depending on the load capacitance. These disadvantages significantly limit the degree of freedom of the logical design.